Nowadays, the vast majority of ICs are realized in complementary metal oxide on silicon (CMOS) technology, because of the high feature density that can be realized in this technology. The reduction in CMOS device feature size has further led to an improvement in the switching speeds of CMOS devices such that it has become feasible, at least in terms of switching speeds, to replace bipolar transistors in high-frequency components of ICs such as radio-frequency (RF) components with CMOS devices. This has the advantage that the number of process steps required for manufacturing the IC can be significantly reduced because it is no longer necessary to have two sets of processing steps for realizing components in different technologies.
However, the speed of the semiconductor device is not the only Figure of Merit (FoM) the designer has to deal with. Other parameters that are at least equally important include maximum frequency of oscillation (fT and fMAX) device, transconductance (gm), output conductance (go), matching, and 1/f noise and NF characteristics.
The required values of these performance parameters are not easily achieved with CMOS devices because the decrease in the feature size of CMOS devices has meant that their supply voltage has also been reduced for reliably operating the device and for reducing the power consumption of the IC. Consequently, the circuit design window has been significantly reduced, which introduces major design problems for e.g. power amplifiers or automotive circuits, for instance because the breakdown voltage of the CMOS devices is insufficient for high-voltage applications.
For analog applications, CMOS devices have been modified in many ways to achieve improved performance. Additional processing steps such as dual oxide technology and drain extensions have been introduced to increase the breakdown voltage of the devices, and additional implants, e.g. halo or pocket implants, have been proposed to counter the short channel effects and to control punch through. Such solutions have the drawback that they need additional process steps and/or additional masks, additional process development and qualification, leading to higher cost of the IC.
It is well known that vertical bipolar transistors are better suited for e.g. high voltage application domains than CMOS devices by virtue of a superior transconductance. Moreover, in a vertical bipolar transistor as suggested by its name, the main current flows vertically through the bulk as opposed to the lateral current flow through the channels of CMOS devices. This makes bipolar transistors much less sensitive to device degradation and allows for high power densities. Exploiting this vertical dimension can yield high breakdown voltages without requiring much extra silicon area compared to a corresponding CMOS device.
However, it is not trivial to manufacture a mixed technology IC. When implementing a manufacturing process with both CMOS and bipolar device manufacturing steps, often either the CMOS device performance suffers when a bipolar process is altered to include CMOS device processing steps, or the bipolar device performance suffers when a CMOS process is altered to include bipolar device processing steps. In addition, both scenarios generally require the inclusion of extra process steps and mask layers, adding to the complexity and cost of the IC manufacturing process.
For this reason, efforts have been undertaken to realize bipolar transistors using CMOS processing steps, since a fully CMOS-process compatible high-performance bipolar transistor device would enable circuit designers to combine the advantages of the (digital) CMOS part with the RF, high-voltage, high-power density and reliability capabilities of bipolar devices in a single technology.
However, the performance characteristics of the available implementations of bipolar devices that are fully compatible with state-of-the art standard CMOS processes i.e. that do not require any additional processing or mask layers to realize the bipolar devices, are significantly inferior to the performance characteristics of bipolar devices realized in dedicated bipolar processes. For instance, one known implementation is a vertical NPN bipolar transistor in CMOS triple-well technology in which the emitter is formed by a highly doped n-type drain region, the base is formed by the p-well and the collector is formed by the buried n-well. However, the thickness of the p-well and its relatively high impurity concentration deteriorate the performance of this bipolar transistor.
Kim et al. in “High Performance NPN BJTs in Standard CMOS process for GSM Receiver and DVB-H Tuner”, IEEE RFIC Symposium, 11-13 Jun. 2006 disclose an improvement of the above bipolar transistor by replacing the p-well with a dedicated implant. This however requires additional mask and processing steps, which are not available in standard CMOS technology, thus significantly increasing the cost of such an IC.